Part of English abbreviations used herein and explanations thereof:
RAM: random access memory;
SRAM: Static RAM;
SDRAM: Synchronous Dynamic RAM;
MAC: Medium Access Control;
DDR: Double Data Rate;
QDR: Quad Data Rate;
FCS: frame check sequence;
CRS: Cyclical Redundancy Check;
FIFO: First input First Output queue;
FPGA: Field Programmable Gate Array;
ASIC: Application Specific Integrated Circuit;
QoS: Quality of Service;
With the popularization of broadband networks on a large scale, the requirement on the performance of a network communication device becomes higher and higher, and the development tendency of network communication devices is towards high performance and high bandwidth utilization rate. As a result, the high-speed network data exchange and traffic management property have become two major functions for network switching devices.
An Ethernet device is a main device in the network switching. To relieve the growing expansion of bandwidth application demands in a data center, a service provider and other traffic-intensive high performance computing environments, the rates for two kinds of new high speed Ethernets, that is, 40G Ethernet and 100G Ethernet, were normalized by the IEEE 802.3ba standard in June 2010, which paves the way for the development of a new wave of higher-speed Ethernet applications.
The Ethernet frame format of the IEEE 802.3ba standard is the same as the frame format of the IEEE802.3 standard. Similar to the XGMII interface of a 10G Ethernet, the media independent interfaces of a 40G Ethernet and a 100G Ethernet are an XLGMII interface and a CGMII interface, the XLGMII and the CGMII both employ eight channels for byte distribution to distribute a 8-bit data signal and a 1-bit control signal on each channel, thus, the bit widths of the interfaces are expanded to 64-bit (8-byte) data and 8-bit control signal. When a control signal is valid, control information is carried on a data line, and when a control signal is invalid, Ethernet valid data is carried on the data line. To perform a logical design at a relatively high clock frequency, the MAC interfaces of a 40G Ethernet and a 100G Ethernet are generally improved in data width and reduced in working frequency. Taking the MAC of a 100G Ethernet as an example, the data width of the MAC is 640 bits, the control bit width of the MAC is 80 bits, and in this case, the operating clock is 156.25 MHz.
To increase the bandwidth utilization rate of existing networks, more and more attention is being paid to the traffic management function of a network device. To provide bandwidth optimization for the fine management of different levels of services, a network device must have a sufficient cache space for supporting the switching capacity under a high bandwidth. In existing network switching devices, the common data memories mainly consist of two kinds of RAMs: SRAM and SDRAM.
Generally, SRAM has a small storage capacity, for example dozens of M bits, and the SRAM can be realized on a chip with low power consumption. SARM is advantaged in simple operation and 100% bandwidth utilization rate; a network switching device using an SRAM as a cache is usually deployed in a layer-2/layer-3 fast switching chip in an Ethernet, and such applications have a particularly high requirement on packet switching speed and a low requirement on storage capacity.
SDRAM generally has a large capacity, and mainly includes DDR and QDR, the currently most advanced DDR3 SDRAM chip is already capable of providing a storage capacity of 8G bits and stably running at a frequency of 2 GHz, thus, SDRAM can provide an extremely high storage capacity and a remarkably large theoretical bandwidth at a low cost. However, because of the structural properties of SDRAM, periodic refreshing is needed, for this and other reasons including tRP, tRFC and other overheads, the actual bandwidth utilization rate is very low. A network switching device using an SDRAM as a cache is generally deployed in chip device such as a layer-2/layer-3 traffic managing and network processing device in an Ethernet.
In a conventional network switching device, for a speed of 10G or below, a structure design for a device based on an SRAM or a DDR SDRAM is usually simple, and the performance of the designed device is satisfactory.
However, the application of a 40G or 100G fast switching device confronts the following problems:
1: The expandability of the conventional caching scheme is poor, which leads to the poor upgradability of a network device. For example, compatibility is unachievable when the bit width of an Ethernet interface is expanded from the 64 bits of an XGMII to the 640 bits of a CGMII;
2: The conventional caching device based on SRAM has a small capacity, and will not be supportive to traffic management and therefore can hardly increase the actual bandwidth utilization rate based on a service;
High-frequency SDRAM, although capable of providing enough actual bandwidth, is high in power consumption, moreover, the peripheral logic design of high-frequency SDRAM is highly difficult; and low-frequency SDRAM is low in actual bandwidth utilization rate because of a high proportion of overheads such as tRP and tRFC. For a device based on the conventional caching scheme, no improvements have been made according to the characteristics of SRDAM, which usually causes a performance bottleneck.